Xueyan Wang

Xueyan Wang

Associate Professor @ School of Integrated Circuit Science and Engineering, Beihang University

Publications

Latest published：

  1. X. Ma et al., “A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration”, 2024 ACM/IEEE Design Automation Conference (DAC). (通讯作者，CCF A 类、集成电路设计自动化领域顶级会议)

  2. Y. Wei et al., “PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator”, 2024 ACM/IEEE Design Automation Conference (DAC). (通讯作者，CCF A 类、集成电路设计自动化领域顶级会议)

  3. Y. Huang et al., “LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators”, accepted by 2024 International Test Conference in Asia (ITC-Asia). (通讯作者，集成电路测试领域著名会议)

  4. S. Zhang et al., “Triangle Counting Acceleration via Content Addressable Memory-Integrated 3D-Stacked Memory”, accepted by 2024 International Test Conference in Asia (ITC-Asia). (通讯作者，集成电路测试领域著名会议)

Conference：

  1. Wei Y, Wang X, Bian S, et al. The-v: Verifiable privacy-preserving neural network via trusted homomorphic execution[C]//2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). IEEE, 2023: 1-9.

  2. Li Y, Zhang H, Wang X, et al. Toward energy-efficient sparse matrix-vector multiplication with near STT-MRAM computing architecture[C]//Proceedings of the 28th Asia and South Pacific Design Automation Conference. 2023: 222-227.

  3. Wang X, Yang J, Zhao Y, et al. TCIM: Triangle counting acceleration with processing-in-MRAM architecture[C]//2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020: 1-6.

  4. Zhao Y, Yang J, Jia X, et al. Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration[C]//2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2019: 203-206.

  5. Wang X, Zhou Q, Cai Y, et al. A conflict-free approach for parallelizing SAT-based de-camouflaging attacks[C]//2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2018: 259-264.

  6. Wang X, Cai Y, Zhou Q. Cell spreading optimization for force-directed global placers[C]//2017 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2017: 1-4.

  7. Wang X, Zhou Q, Cai Y, et al. An empirical study on gate camouflaging methods against circuit partition attack[C]//Proceedings of the on Great Lakes Symposium on VLSI 2017. 2017: 345-350.

  8. Wang X, Zhou Q, Cai Y, et al. Is the secure IC camouflaging really secure?[C]//2016 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2016: 1710-1713.

  9. Wang X, Jia X, Zhou Q, et al. Secure and low-overhead circuit obfuscation technique with multiplexers[C]//Proceedings of the 26th edition on Great Lakes Symposium on VLSI. 2016: 133-136.

  10. Zhou Q, Wang X, Qi Z, et al. An accurate detailed routing routability prediction model in placement[C]//2015 6th Asia Symposium on Quality Electronic Design (ASQED). IEEE, 2015: 119-122.

Journal：

  1. Li Y, Wang X, Zhang H, et al. Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems[J]. ACM Transactions on Embedded Computing Systems, 2024, 23(3): 1-24.

  2. Duan C, Yang J, Wang Y, et al. Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity[J]. arXiv preprint arXiv:2404.09497, 2024.

  3. Li Y, Wang J, Zhu D, et al. APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-level Operations of Quantized Convolutional Neural Networks[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024.

  4. Lu Z, Wang X, Arafin M T, et al. An RRAM-Based Computing-in-Memory Architecture and Its Application in Accelerating Transformer Inference[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023.

  5. Duan C, Yang J, He X, et al. DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023.

  6. Gu H, Jia X, Liu Y, et al. CiM-BNN: Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network[J]. IEEE Transactions on Emerging Topics in Computing, 2023.

  7. WANG X, CHEN X, JIA X, et al. Graph Algorithm Optimization for Spintronics-based In-memory Computing Architecture[J]. 电子与信息学报, 2023, 45(9): 3193-3199.

  8. Wei Y, Wang X, Zhang S, et al. Imga: Efficient in-memory graph convolution network aggregation with data flow optimizations[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 42(12): 4695-4705.

  9. Jia X, Gu H, Liu Y, et al. An energy-efficient Bayesian neural network implementation using stochastic computing method[J]. IEEE Transactions on Neural Networks and Learning Systems, 2023.

  10. Zhao Y, Yang J, Li B, et al. NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration[J]. Science China Information Sciences, 2023, 66(4): 142401.

  11. Hou Z, Wang Z, Wang C, et al. Reconfigurable and dynamically transformable in-cache-MPUF system with true randomness based on the SOT-MRAM[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(7): 2694-2706.

  12. Chen X, Wang X, Jia X, et al. Accelerating graph-connected component computation with emerging processing-in-memory architecture[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41(12): 5333-5342.

  13. Wang X, Yang J, Zhao Y, et al. Triangle counting accelerations: From algorithm to in-memory computing architecture[J]. IEEE Transactions on Computers, 2021, 71(10): 2462-2472.

  14. Pan Y, Jia X, Cheng Z, et al. An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing[J]. CCF Transactions on High Performance Computing, 2020, 2: 272-281.

  15. Wang X, Yang J, Zhao Y, et al. Hardware security in spin-based computing-in-memory: Analysis, exploits, and mitigation techniques[J]. ACM Journal on Emerging Technologies in Computing Systems (JETC), 2020, 16(4): 1-18.

  16. Jia X, Yang J, Liu R, et al. Efficient computation reduction in Bayesian neural networks through feature decomposition and memorization[J]. IEEE transactions on neural networks and learning systems, 2020, 32(4): 1703-1712.

  17. Wang X, Zhou Q, Cai Y, et al. Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding[J]. Integration, 2019, 67: 108-120.

  18. Jiang S, Xu N, Wang X Y, et al. An efficient technique to reverse engineer minterm protection based camouflaged circuit[J]. Journal of Computer Science and Technology, 2018, 33: 998-1006.

  19. Wang X, Zhou Q, Cai Y, et al. Toward a formal and quantitative evaluation framework for circuit obfuscation methods[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 38(10): 1844-1857.

  20. Yang J, Wang X, Zhou Q, et al. Exploiting spin-orbit torque devices as reconfigurable logic for circuit obfuscation[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 38(1): 57-69.

  21. Wang X Y, Zhou Q, Cai Y C, et al. Spear and shield: Evolution of integrated circuit camouflaging[J]. Journal of Computer Science and Technology, 2018, 33: 42-57.

  22. Wang X, Gao M, Zhou Q, et al. Gate camouflaging-based obfuscation[J]. Hardware Protection Through Obfuscation, 2017: 89-102.